Description:

This book offers a practical, application-oriented introduction to Digital Hardware Modelling using SystemVerilog. Written in a student-friendly style adopting a step-by-step learning approach, the book simplifies the nuances of language constructs and design methodologies, empowering readers to design Application Specific Integrated Circuits (ASICs), System on Chip (SoC), and Central Processing Unit (CPU) architectures. It covers a broad spectrum of topics, including SystemVerilog assertions, functional coverage, interfaces, mailboxes, and various data types—presented with clarity and supported by easy-to-follow examples.

Authored by an experienced professor and practitioner of ASIC/SoC/CPU and FPGA design, this book is grounded in hands-on experience and real-world application. The extensive coding examples demonstrate using a wide range of SystemVerilog constructs, making this a valuable reference for tackling complex, multi-million-gate ASIC design challenges.

It serves as a comprehensive guide for students, educators, and professionals who want to master the SystemVerilog language and apply it in real-world VLSI design environments. Overall, the book helps readers understand the role of modelling in chip fabrication.

KEY FEATURES

• Covers every aspect of SystemVerilog, from introducing Modelling and SystemVerilog Hardware Description Language to Modelling a Processor in SystemVerilog.

• Includes several coding examples to help students to model different digital hardware.

• Covers the concepts of data path and control path, frequently used in processor chips.

• Explains the concept of pipelining, used in the processor.

TARGET AUDIENCE

• B.Tech Electronics, Electronics and Communication Engineering

• B.Tech Computer Science and Computer Applications

• Front-End Engineers.